In current semiconductor products, memory-merged logic is popular for a variety of memory configurations, including, for example, dynamic random access memory (DRAM), static random access memory (SRAM), flash memory and the like embedded on a single chip. For memory merged logic developed as a system-on-chip, as the degree of integration of embedded memory devices increases, for example to over 1M-bits of memory cells on a single chip, redundant memory cells have become popular in such systems.
Testing procedures are applied to memory-merged logic systems in order to determine the presence of defects in the memory cells of the embedded memory devices. For example, an Electrical Die Shorting (EDS) process may be employed. In this process, a probe connected to a tester system makes electrical connection with the embedded memory devices of the memory merged logic through a probing pad at the time of the memory tests.
Under conventional testing procedures, the respective tests are separately performed for the different embedded memory devices, such as DRAM, SRAM, flash memory and the like. Thus, test pins are allotted, without any consideration of the use of the pins, such as input, output and input/output pins, so that it has been possible to carry out separate tests for respective embedded memory devices. As such EDS tests are performed, the probe comes in contact with a probing pad a multiple number of times. Such high probing frequency tends to damage the probing pads, which in turn can lead to an decrease in the yield percentage of the semiconductor products.